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VCXO-TO-LVCMOS OUTPUTS
ICS81006I
GENERAL DESCRIPTION
The ICS81006I is a high performance, low jitter/ IC S low phase noise VCXO and is a member of the HiPerClockSTM HiPerClockSTM family of high performance clock solutions from IDT. The ICS81006I works in conjunction with a pullable crystal to generate an output clock over the range of 12MHz - 40MHz and has 6 LVCMOS outputs, effectively integrating a fanout buffer function. The frequency of the VCXO is adjusted by the VC control voltage input. The output range is 100ppm around the nominal crystal frequency. The VC control voltage range is 0 - V DD . The device is packaged in a small 4mm x 4mm VFQFN package and is ideal for use on space constrained boards typically encountered in ADSL/VDSL applications.
FEATURES
* Six LVCMOS/LVTTL outputs, 20 nominal output impedance * Output Q5 can be selected for /1 or /2 frequency relative to the crystal frequency * Output frequency range: 12MHz to 40MHz * Crystal pull range: 90ppm (typical) * Synchronous output enable places outputs in High-Z state * On-chip filter on VIN to suppress noise modulation of VCXO * VDD/VDDO combinations 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V * 4mm x 4mm 20 Lead VFQFN package is ideal for space constrained designs * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
OE0 (Pullup)
PIN ASSIGNMENT
GND VDDO OE0
SYNC
Q0
VC
LP Filter
XTAL_IN XTAL_OUT
1 2 3 4 5
20 19 18 17 16 15 14 13 12 6
OE1
Q0
Q1
GND Q2 VDDO Q3 GND
Q1 XTAL_IN
VDD VC
VCXO
Q2 XTAL_OUT Q3
DIV_SEL_Q5
7
GND
8
Q5
9
VDDO
11 10
Q4
ICS81006I
Q4
20-Lead VFQFN 4mm x 4mm x 0.95 package body K Package Top View
0: /1 1: /2 DIV_SEL_Q5 (Pulldown)
Q5
OE1
(Pullup)
SYNC
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TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3 4 Name XTAL_IN, XTAL_OUT VDD VC Type Input Power Input Description Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Core supply pin.
Control voltage input. Output divider select pin for Q5 output. When LOW, /1. When HIGH, 5 DIV_SEL_Q5 Input Pulldown /2, LVCMOS/LVTTL interface levels. Output enable pin. When HIGH, Q5 output is enabled. 6 OE1 Input Pullup When LOW, forces Q5 to HiZ state. LVCMOS/LVTTL interface levels. 7 , 1 1, 1 5 , 1 9 GND Power Power supply ground. 8 , 1 0, 12, Q5, Q4, Q3, Single-ended clock outputs. LVCMOS/LVTTL interface levels. Output 14, 16, 18 Q2, Q1, Q0 15 typical output impedance. Power Output supply pins. 9, 13, 17 VDDO Output enable pin. When HIGH, Q0:Q4 outputs are enabled. When 20 OE0 Input Pullup LOW, forces Q0:Q4 to HiZ state. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN Parameter Input Capacitance OE0, OE1 VDD = VDDO = 3.465V CPD Power Dissipation Capacitance VDD = 3.465V or 2.625V, VDDO = 2.625V VDD = 3.465V or 2.625V, VDDO = 2V RPULLUP RPULLDOWN ROUT Input Pullup Resistor Input Pulldown Resistor VDDO = 3.3V Output Impedance VDDO = 2.5V VDDO = 1.8V 51 51 20 25 38 Test Conditions Minimum Typical 4 3 4 6 Maximum Units pF pF pF pF k k
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 60.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 3.3V5% = 2.5V5% = 1.8V0.2V, TA = -40C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 2.375 1.6 Typical 3.3 3.3 2.5 1.8 Maximum 3.465 3.465 2.625 2.0 50 20 Units V V V V mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 2.5V5% = 1.8V0.2V, TA = -40C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 1.6 Typical 2.5 2. 5 1.8 Maximum 2.625 2.625 2.0 50 20 Units V V V mA mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40C TO 85C
Symbol VIH VIL VC IIH IIL II VOH Parameter Input High Voltage Input Low Voltage OE0, OE1, DIV_SEL_Q5 DIV_SEL_Q5 OE0, OE1 DIV_SEL_Q5 OE0, OE1 Test Conditions VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.465V or 2.625V VDDO = 3.3V 5% Output High Voltage;NOTE 1 VDDO = 2.5V 5% VDDO = 1.8V 0.2V VOL Output Low Voltage;NOTE 1 VDDO = 3.3V or 2.5V 5% VDDO = 1.8V 0.2V -5 -150 -100 2.6 1.8 1.5 0.5 0.4 100 Minimum 2 1.7 -0.3 -0.3 0 Typical Maximum VDD + 0.3 VDD + 0.3 0. 8 0.7 VDD 150 5 Units V V V V V A A A A A V V V V V
VCXO Control Voltage Input High Current Input Low Current
Input Current of VC pin
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
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TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Q0:Q4 Output Skew; NOTE 2, 3 Q0:Q5 Output Rise/Fall Time Test Conditions Minimum 12 Integration Range: 1kHz- 1MHz Typical 19.44 0.35 30 DIV_SEL_Q5 = /1 20% to 80% 200 100 750 56 Maximum 40 Units MHz ps ps ps ps %
tjit(O)
tsk(o) t R / tF
odc Output Duty Cycle 44 NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Q0:Q4 Output Skew; NOTE 2, 3 Q0:Q5 Output Rise/Fall Time Test Conditions Minimum 12 Integration Range: 1kHz- 1MHz Typical 19.44 0.38 20 DIV_SEL_Q5 = /1 20% to 80% 300 90 800 55 Maximum 40 Units MHz ps ps ps ps %
tjit(O)
tsk(o) t R / tF
odc Output Duty Cycle 45 NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Q0:Q4 Output Skew; NOTE 2, 3 Q0:Q5 Output Rise/Fall Time Test Conditions Minimum 12 Integration Range: 1kHz-1MHz Typical 19.44 0.27 50 DIV_SEL_Q5 = /1 20% to 80% 450 180 1400 55 Maximum 40 Units MHz ps ps ps ps %
tjit(O)
tsk(o) t R / tF
odc Output Duty Cycle 45 NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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TABLE 4D. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Q0:Q4 Output Skew; NOTE 2, 3 Q0:Q5 Output Rise/Fall Time Test Conditions Minimum 12 Integration Range: 1kHz-1MHz Typical 19.44 0.28 25 DIV_SEL_Q5 = /1 20% to 80% 300 105 800 55 Maximum 40 Units MHz ps ps ps ps %
tjit(O)
tsk(o) t R / tF
odc Output Duty Cycle 45 NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4E. AC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Q0:Q4 Output Skew; NOTE 2, 3 Q0:Q5 Output Rise/Fall Time Test Conditions Minimum 12 Integration Range: 1kHz-1MHz Typical 19.44 0.26 40 DIV_SEL_Q5 = /1 20% to 80% 450 185 1400 60 Maximum 40 Units MHz ps ps ps ps %
tjit(O)
tsk(o) t R / tF
odc Output Duty Cycle 40 NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5% VDD, VDDO
Qx
SCOPE
VDD VDDO
GND Qx
SCOPE
LVCMOS
GND
LVCMOS
-1.65V5% -1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.4V0.065V 0.9V0.1V
1.25V5%
VDD VDDO
GND Qx
SCOPE
VDD, VDDO
Qx
SCOPE
LVCMOS
GND
LVCMOS
-0.9V0.1V
-1.25V5%
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
1.6V0.025V 0.9V0.1V
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
VDD VDDO
GND Qx
SCOPE
Phase Noise Mask
LVCMOS
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-0.9V0.1V
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
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V
DDO
V
DD
Qx
2
Q0:Q5 t PW
V
t
DDO
2
PERIOD
Qy
2 tsk(o)
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% 20% tR
80% 20% tF
Clock Outputs
OUTPUT RISE/FALL TIME
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APPLICATION INFORMATION
VCXO CRYSTAL SELECTION
Choosing a crystal with the correct characteristics is one of the most critical steps in using a Voltage Controlled Crystal Oscillator (VCXO). The crystal parameters affect the tuning range and accuracy of a VCXO. Below are the key variables and an example of using the crystal parameters to calculate the tuning range of the VCXO.
VC
CV
Oscillator
Control Voltage
VCXO (Internal)
XTAL
C
V
CS1
CS2
FIGURE 1: VCXO OSCILLATOR CIRCUIT
VC Control voltage used to tune frequency CV Varactor capacitance, varies due to the change in control voltage
TABLE 5. EXAMPLE CRYSTAL PARAMETERS
Symbol fN fT fS CL CO C0, C1 ESR Parameter Nominal Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Aging @ 25C Mode of Operation 3 per year Fundamental 0 12 4 220 240 20 1 mW ppm Test Conditions Minimum Typical 19.44 20 20 70 Maximum Units MHz ppm ppm C pF pF
IDT TM / ICSTM VCXO-TO-LVCMOS OUTPUTS
CL1
Optional
CL2
CL1, CL2 Load tuning capacitance used for fine tuning or centering nominal frequency CS1, CS2 Stray Capacitance caused by pads, vias, and other board parasitics
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TABLE 6. VARACTOR PARAMETERS
Symbol CV_LOW CV_HIGH Parameter Low Varactor Capacitance High Varactor Capacitance Test Conditions VC = 0V VC = 3.3V Minimum Typical 15.4 29. 6 Maximum Units pF pF
FORMULAS
C Low =
(C (C
L1
L1
+ C S 1 + CV _ Low ) + (C L 2 + C S 2 + CV _ Low )
+ C S 1 + CV _ Low ) (C L 2 + C S 2 + CV _ Low )
C High =
(C (C
L1 + C S 1 + CV _ High ) + (C L 2 + C S 2 + CV _ High )
L1
+ C S1 + CV _ High ) (C L 2 + C S 2 + CV _ High )
* CLow is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance. CLow determines the high frequency component on the TPR. * CHigh is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance. CHigh determines the low frequency component on the TPR.
1 1 10 6 Total Pull Range (TPR ) = - C 0 1 + C Low 2 C 0 1 + C High 2 C1 C0 C1 C0
Absolute Pull Range (APR) = Total Pull Range - (Frequency Tolerance + Frequency Stability + Aging)
EXAMPLE CALCULATIONS
Using the tables and figures above, we can now calculate the TPR and APR of the VCXO using the example crystal parameters. For the numerical example below there were some assumptions made. First, the stray capacitance (CS1, CS2), which is all the excess capacitance due to board parasitic, is 4pF. Second, the expected lifetime of the project is 5 years; hence the inaccuracy due to aging is 15ppm. Third, though many boards will not require load tuning capacitors (CL1, CL2), it is recommended for long-term consistent performance of the system that two tuning capacitor pads be placed into every design. Typical values for the load tuning capacitors will range from 0 to 4pF.
CLow =
(0 + 4 pf + 15.4 pf ) (0 + 4 pf + 15.4 pf ) = 9.7 pf (0 + 4 pf + 15.4 pf ) + (0 + 4 pf + 15.4 pf )
CHigh =
(0 + 4 pf + 29.6 pf ) (0 + 4 pf + 29.6 pf ) = 16.8 pf (0 + 4 pf + 29.6 pf ) + (0 + 4 pf + 29.6 pf )
1 1 106 = 226.5 ppm - TPR = 2 220 1 + 16.8 pF 2 220 1 + 9.7 pF 4 pF 4 pF
TPR = 113.25ppm APR = 113.25ppm - (20ppm + 20ppm + 15ppm) = 58.25ppm
The example above will ensure a total pull range of 113.25 ppm with an APR of 58.25ppm. Many times, board designers may select their own cr ystal based on their application. If the application requires a tighter APR, a crystal
with better pullability (C0/C1 ratio) can be used. Also, with the equations above, one can vary the frequency tolerance, temperature stability, and aging or shunt capacitance to achieve the required pullability.
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: INPUTS:
CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. The VC pin can not be floated. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached.
SCHEMATIC EXAMPLE
Figure 2 shows an example of ICS81006I application schematic. The decoupling capacitors should be located as close as possible to the power pin. For the LVCMOS 20 output drivers,
series termination example is shown in the schematic. Additional termination approaches are shown in the LVCMOS Termination Application Note.
Pull-up VDD example
VDDO
Quartz crystal should be placed as close to the device as possible.
C1 SPARE
R4 1K VDD 20 19 18 17 16 R1 Zo = 50 30 U1
XTAL
1 2 3 4 5
OE0 GND Q0 VDDO Q1
VC = 0V to VDD
VC 81006 81006I Pull-down example R3 1K
6 7 8 9 10
OE1 GND Q5 VDDO Q4
C2 SPARE
XTAL_IN XTAL_OUT VDD VC DIV_SEL_Q5
GND Q2 VDDO Q3 GND
15 14 13 12 11
R2 Zo = 50 VDD 30 R5 1K
(U1-3)
VDD
(U1-9)
VDDO
(U1-13)
(U1-17)
C7 10uf
C6 0.1uF
C5 0.1uF
C4 0.1uF
C3 0.1uF
Unused outputs can be left floating. There should be no trace attached to unused outputs. Device characterized and specification limits set with all outputs terminated.
FIGURE 2. ICS81006I SCHEMATIC EXAMPLE
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
20 LEAD VFQFN
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 60.4C/W
1
52.8C/W
3
46.0C/W
TRANSISTOR COUNT
The transistor count for ICS81006I is: 983
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PACKAGE OUTLINE - K SUFFIX FOR 20 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS FOR 20 LEAD VFQFN
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.75 0.35 0.75 4.0 2.80 0.75 0.18 0.50 BASIC 5 5 4.0 2.80 0.80 0 0.25 Reference 0.30 MINIMUM 20 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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TABLE 9. ORDERING INFORMATION
Part/Order Number ICS81006AKI ICS81006AKIT ICS81006AKILF ICS81006AKILFT Marking 1006AI 1006AI TBD TBD Package 20 lead VFQFN 20 lead VFQFN 20 lead "Lead-Free" VFQFN 20 lead "Lead-Free" VFQFN Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
netcom@idt.com 480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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